1. Field of the Invention
The present invention relates to a counter for counting periods of an input signal during a reference period. In particular, the present invention relates to a counter comprising additional circuitry for correcting a count value to provide improved precision.
2. Discussion of the Related Art
In order to measure the frequency of an input oscillating signal, for example the square-wave output of a voltage controlled oscillator (VCO), a counter can be used. During a known reference time period, generally provided by a high quality quartz oscillator that generates clean timing edges, a counter counts the number of periods of the input oscillating signal. The frequency f can then be determined as:f=count/tREF 
where “count” is the count value reached by the counter during the reference period and tREF is the duration of the reference time period.
Counters are limited, however, in that they generally count either the rising or falling edges of an input signal, and when the start and end times of the reference period are not close to the relevant edge of the input signal, the count value will be inaccurate. There is thus an inherent inaccuracy in the count value which can be as high as nearly two counts of the counter. The frequency f of the input signal is thus:f=(count+ε)/tREF 
where ε is the count error with 0<ε<2.
One way of reducing the effect of this error is to increase the reference time period so that the count is higher and the error ε becomes less significant. However according to this solution the time needed to calculate the input frequency is increased, and this is not compatible for applications in which a result from the counter is required quickly.
FIG. 1 illustrates a known method of increasing the accuracy of the counter without increasing the reference time period. Such a method is described, for example, in “A digitally controlled PLL for SoC applications”, T. Olsson and P. Nilsson, IEEE Solid-State Circuits, vol. 39, no. 5, pp. 751-760, May 2004.
As shown in FIG. 1, a circuit comprises two counters, a first counter 2 which counts rising edges of an input signal, and a second counter 4 which counts the falling edges of the input signal. The input signal is provided to each counter on an input line 6. The first and second counters 2, 4 are controlled to count the rising and falling edges respectively of the input signal during the reference time period. The output of each counter is provided to an adder 8 which adds the counts together to provide a combined count value on output line 10, which represents the number of half periods of the input signal. The error ε is therefore halved, and the frequency can be determined as:f=0.5(combined count+ε)/tREF 
One disadvantage of the circuit of FIG. 1 is that two counters are required instead of one. In practice, to achieve a sufficiently accurate frequency estimation, thousands of periods of the input signal are counted, and therefore the counters are for example 12-bit or 15-bit counters, which require a relatively significant chip area. There is thus a need for a counter that provides improved accuracy over the single counter solution described above, without requiring a second counter and without increasing the reference time period.